A portion of a memory array of a conventional semiconductor memory having a two-transistor or 2T architecture or memory structure is shown in FIG. 1. Referring to FIG. 1 the portion of the memory array 102 includes four memory cells 104 arranged in two rows (ROW 0, ROW 1) and two columns (COL0, COL1). Each of the memory cells includes a non-volatile memory transistor 106, and a pass or select transistor 108 sharing a common substrate connection 110 with the memory transistor. The memory transistor 106 generally includes a charge trapping layer 112, a drain 114 connected to a bitline 116, a source 118 connected through the select transistor 108 to a source-line 120, and a control gate 122 connected to a control line or memory line 124. Select transistor 108 also includes a drain 126 connected to the source 118 of the memory transistor 106, a source 128 connected to the source-line 120, and a gate 130 connected to a wordline (WL) 132.
Referring to FIG. 2A, it is seen that each cell (202 and 204) in a conventional 2T memory structure includes a dedicated source-line (SL0 and SL1) formed from a first metal layer formed over or near diffusion regions 206, 208, in a surface of a substrate 210 in which active devices (transistors) of the memory cell are formed, and a bitline (BL0, BL1) formed from a second metal layer formed over a first or upper inter-level dielectric layer 212 separating the second metal layer from the source-lines (SL0 and SL1). Typically, as shown in FIG. 2B, the bitlines (BL0 and BL1) are electrically coupled to drains 214 of memory transistors in each cell (202 and 204) through first vias 216 and an island or pad 218 formed from the first metal layer, and second or lower vias 220 formed through a second or lower inter-level dielectric layer 222. The source-lines (SL0 and SL1) are also electrically coupled to sources (not shown in this figure) of select transistors in each cell (202 and 204) through lower vias extending through the lower inter-level dielectric layer 222. Thus, one problem with the conventional 2T memory structure is that despite advances in technology, which have enabled the size of active elements in the memory cell to be reduced to 65 nanometers (nm) and beyond, the reduction in pitch or spacing of adjacent memory cells in adjoining columns is limited by the width of the pad 218, the dedicated source-lines (SL0 and SL1) in each cell, and a spacing therebetween.
Another problem with conventional 2T architecture is that during programming the dedicated source-lines in non-selected memory cells or columns of memory cells are biased to or held at a potential that increases power consumption of the memory array.
Thus, there is a need for an improved memory structure as well as a method of operating the same.